S/390 CMOS Cryptographic Coprocessor Architecture: Overview and design considerations
نویسندگان
چکیده
This paper describes the design objectives and presents an overview of the design for the IBM S/390T CMOS Cryptographic Coprocessor, also known as the S/390 cryptographic module (SCM). The SCM is fully compatible with the earlier S/390 cryptographic module, ICRF (Integrated Cryptographic Facility), and has been certified by the National Institute of Standards and Technology at the highest level of security qualification. The principal features and unique characteristics of the SCM are summarized in the context of the architecture design.
منابع مشابه
S/390 Parallel Enterprise Server CMOS Cryptographic Coprocessor
As the Internet becomes the basis for electronic commerce, and as more businesses automate their data processing operations, the potential for unauthorized disclosure of sensitive data increases. On-line databases are becoming increasingly large and complex. Sensitive data is transmitted on communication lines and often stored off-line. As a result, the efficient, economical protection of enter...
متن کاملA Side-Channel Leakage Free Coprocessor IC in 0.18μm CMOS for Embedded AES-based Cryptographic and Biometric Processing
Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption and other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC and its design techniques. The IC has been fabricated in 0.18μm CMOS. The coprocessor, which is used for embedded cryptogra...
متن کاملSubterranean: A 600 Mbit/Sec Cryptographic VLSI Chip
In this paper the design of a high-speed cryptographic coprocessor is presented. This coprocessor is named Subterranean and can be used for both cryptographic pseudorandom sequence generation (Substream) and cryptographic hashing (Subhash). In Substream mode the chip can be used for stream encryption/decryption under control of a 256-bit key. A cryptographic resynchronization mechanism is provi...
متن کاملA 1.96mm2 low-latency multi-mode crypto-coprocessor for PKC-based IoT security protocols
In this paper, we present the implementation of a multi-mode crypto-coprocessor, which can support three different public-key cryptography (PKC) engines (NTRU, TTS, Pairing) used in post-quantum and identity-based cryptosystems. The PKC-based security protocols are more energy-efficient because they usually require less communication overhead than symmetric-key-based counterparts. In this work,...
متن کامل— G 5 and G 6 performance considerations
The CMOS-based IBM S/390 Parallel Enterprise Servers have always employed the technique of memory caching to bridge the gap between processor speed and mainmemory access time. However, that gap has widened with each succeeding system generation, requiring increasingly sophisticated, multiple-level cache structures in order to minimize memory-access latency. The IBM S/390 G5 and G6 include two-l...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- IBM Journal of Research and Development
دوره 43 شماره
صفحات -
تاریخ انتشار 1999